The present invention concerns netlist extraction during layout design of an integrated circuit. Particularly, the present invention pertains to automated extraction of source and drain resistance for transistors used in the integrated circuit.
In the course of the design of very large scale integrated (VLSI) circuits it is desirable to perform circuit characterization to determine circuit performance. The characterization of VLSI circuits is heavily dependent on parasitic resistance and parasitic capacitance. A circuit extraction system, (also called a netlist extractor) is used to extract from a circuit design particular circuits to be simulated. The extraction includes not only the circuitry, but also the parasitic capacitance and parasitic resistance inherent in circuit components.
In the past, various methods have been used to determine parasitic resistance for the source and drain. For example, in one prior art system, gate resistivity is assumed to be five to ten times the source/drain resistivity. The gate region and the source drain regions are broken up into about twenty pieces. Resistance is calculated for each piece and a resistance mesh is formed. A voltage is applied across the two ends of the mesh and the resulting current obtained. The total resistance is calculated by dividing the applied voltage by the resulting current. The source/drain region resistance is determined by subtracting out the gate resistance from the total resistance. See G. Yokomizo, A. Yajima, Y. Okamura, T. Sato, HICE; Hierarchical Circuit Extraction System for Layout Verification, Proceedings of the IEEE Custom Integrated Circuits Conference, 1987, pp. 133-136. This system assumes a fixed gate resistivity independent of the layout. Further, this solution neglects two dimensional effects by assuming current flow in a region to be one dimensional.
In another prior art system, a technique is used to calculate the distributed resistance of multi-regional arbitrary geometries. The technique makes use of an extended complex potential method. See Y. Okamura, Y. Muraishi, T. Sato, and Y. Ikemoto, LAS: Layout Pattern Analysis System with New Approach, ICCC, 1982, pp. 308-311. This system solves Laplace's equation numerically, however, this is not done with a standard numerical technique, e.g., finite element or finite difference. Also the equations used are solved for the case of a single fixed gate resistivity independent of layout.